`include "cpu_def.vh"

module forward (
  input        wb_rf_wen  ,
  input [ 4:0] wb_rf_wnum ,
  input [31:0] wb_rf_wdata,

  input        ex_rf_wen  ,
  input [ 4:0] ex_rf_wnum ,
  input [31:0] ex_rf_wdata,
  
  input [ 4:0] de_rs      ,
  input [ 4:0] de_rt      ,

  output [ 1:0] de_sel_rf_rdata_0,  // forward data select
                                    //* 00: rdata from regfile
                                    //* 01: forward_data_ex
                                    //* 10: forward_data_wb
  output [ 1:0] de_sel_rf_rdata_1,
  output [31:0] forward_data_ex  ,
  output [31:0] forward_data_wb  
);

  wire de_ex_rs_rel = ex_rf_wen && de_rs != 5'd0 && de_rs == ex_rf_wnum;
  wire de_ex_rt_rel = ex_rf_wen && de_rt != 5'd0 && de_rt == ex_rf_wnum;
  wire de_wb_rs_rel = wb_rf_wen && de_rs != 5'd0 && de_rs == wb_rf_wnum;
  wire de_wb_rt_rel = wb_rf_wen && de_rt != 5'd0 && de_rt == wb_rf_wnum;

  assign de_sel_rf_rdata_0[0] = 
    de_ex_rs_rel;
  assign de_sel_rf_rdata_0[1] = 
    de_wb_rs_rel && !de_ex_rs_rel;
  assign de_sel_rf_rdata_1[0] = 
    de_ex_rt_rel;
  assign de_sel_rf_rdata_1[1] = 
    de_wb_rt_rel && !de_ex_rt_rel;
  assign forward_data_ex = ex_rf_wdata;
  assign forward_data_wb = wb_rf_wdata;

endmodule
